1. Field of the Invention
The present invention relates to fabrication methods of semiconductor packages, and more particularly, to a fabrication method of a wafer level semiconductor package and a fabrication method of a wafer level packaging substrate for improving the product accuracy.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To meet the miniaturization requirement of semiconductor packages, wafer level packaging (WLP) technologies have been developed.
U.S. Pat. No. 6,452,265 and U.S. Pat. No. 7,202,107 provide fabrication methods of wafer-level packages. FIGS. 1A to 1E are schematic cross-sectional views showing a fabrication method of a conventional wafer level semiconductor package 1.
Referring to FIG. 1A, a thermal release tape 11 is formed on a carrier 10.
Referring to FIG. 1B, a plurality of semiconductor components 12 are disposed on the thermal release tape 11. Each of the semiconductor components 12 has an active surface 12a with a plurality of electrode pads 120 and an inactive surface 12b opposite to the active surface 12a. Each of the semiconductor components 12 is disposed on the thermal release tape 11 via the active surface 12a thereof.
Referring to FIG. 1C, an encapsulant 13 is formed on the semiconductor components 12 and the thermal release tape 11 through molding.
Referring to FIG. 1D, the thermal release tape 11 and the carrier 10 are removed to expose the active surfaces 12a of the semiconductor components 12.
Referring to FIG. 1E, by performing a redistribution layer (RDL) process and a bump process, a circuit structure 14 is formed on the encapsulant 13 and the active surfaces 12a of the semiconductor components 12 and electrically connecting the electrode pads 120 of the semiconductor components 12.
However, since the thermal release tape 11 is flexible, the positioning accuracy of the semiconductor components 12 is adversely affected by the CTE (Coefficient of Thermal Expansion) of the thermal release tape 11 and lateral forces applied on the thermal release tape 11 by the encapsulant 13 during the molding process. Therefore, an increase in the size of carrier 10 results in an increase in the position error of the semiconductor components 12, thereby causing yield losses in the RDL and bump processes.
Furthermore, since the above-described method forms the encapsulant 13 before performing the RDL process, if it is detected that the circuit structure 14 is of low quality during a subsequent test, the overall semiconductor package 1 has to be discarded. That is, good semiconductor components 12 are also discarded, thus resulting in a high fabrication cost. Therefore, the above-described method is not economic.
Therefore, how to overcome the above-described drawbacks has become critical.